The present invention relates to an instruction precontrol system for a data processing unit, and more particularly to a data processing unit having an instruction precontrol function which is suitable in executing a mode set/unconditional branch instruction (BSM instruction) and a mode set/unconditional branch/link instruction (BASSM instruction).
When the memory capacity in a general purpose data processing unit has been increased, a 24-bit operand address is no longer large enough. An architecture which can process an operand address of 31 bits or more is adopted. In this case, it is necessary that a program resource of the 24-bit architecture can also be used as desired. To this end, the data processing unit for this purpose is provided with the mode set/unconditional branch instruction (BSM instruction) and the mode set/unconditional branch/link instruction (BASSM instruction) to allow switching of the address mode between 24 bits mode and 31 bits mode.
The BSM instruction allows setting of a new address mode in an address mode bit of a program status word (PSW) and execution of a program by unconditional branch in the new address mode. The BASSM instruction has, in addition to the function of the BSM instruction, a link function to allow return to the original program when a branched program has been executed. By the provision of the BSM instruction or the BASSM instruction, program resources of different address modes can be executed in one data processing unit.
FIG. 2 shows the format of the BSM and the BASSM instructions. Since the BSM instruction and the BASSM instruction are identical except for the link function, only the BSM function is explained here. In FIG. 2, when an operation code indicates the BSM instruction code, a content of an address mode bit in a current PSW is loaded to a bit 0 position of a general purpose register designated by an R1 field in a register field of the instruction. Then, a content of a bit 0 position of a general purpose register designated by an R2 field is newly set to an address mode bit of the PSW, and a branch address is generated based on the content of the bits 1-31 of that general purpose register and it is set into a program counter. The branch address is calculated in the following manner. When the newly set address mode bit is "0" (which indicates the 24-bit architecture), the branch address is equal to the content of the bits 8-31 of the general purpose register designated by the R2 field with 0's being added to the high order 8 bits. When the newly set address mode bit is "1" (which indicates the 31-bit architecture), the branch address is equal to the content of the bits 1-31 of the general purpose register designated by the R2 field with 0's being added to high order 1 bit.
In the data processing unit having the instruction precontrol function, the calculation of the branch address is carried out in a preexecution cycle in accordance with the current address mode designated by the PSW. Accordingly, if the address mode of the PSW in the preexecution cycle and the address mode newly set in the PSW in the execution cycle of the instruction are different, it is necessary to provide an operand address calculation cycle between the instruction execution cycles to recalculate the address.
JP-A-62-11939 discloses a method for improving an execution function of the BSM instruction and the BASSM instruction by omitting the recalculation of the address. In this method, when the instruction decoded in the preexecution cycle is the BSM instruction or the BASSM instruction, branch addresses for the respective modes are calculated in the preexecution cycle, and one of the precalculated addresses is selected in accordance with the address mode which is set in the PSW in the execution cycle of the instruction and it is used as the branch address for the new address mode.
In the prior art method, the branch addresses for both the 24-bit address and the 31-bit address are calculated in the preexecution cycle independently from the address mode bit of the current PSW, and after the address mode has been determined in the execution cycle of the instruction, one of the addresses is selected to determine the branch destination address. Accordingly, fetching of a branch destination instruction cannot be started until the address mode is determined and the correct branch destination address is determined.